SEU effects in registers and in a Dual-Ported Static RAM designed in a 0.25 μm CMOS technology for applications in the LHC

A dedicated high-speed 18 Kbit static memory featuring synchronous mode, parity and dual port access has been designed and fabricated in a quarter micron 3 metals commercial CMOS technology. This SRAM has been designed to be a test vehicle to measure Single Event Upset (SEU) effects on a real circuit. The measurements have been performed at the cyclotron of Louvain-la-Neuve, Belgium, with a proton and heavy ion beam. We present the experimental cross-section curve for the RAM chip, together with a detailed study of the SEU phenomenon on dedicated test structures (shift registers) integrated in the same technology. Finally, we give an estimate for the upset rate the memory chip will experience in LHC.